In line with the recent trends of downsizing and introduction of higher frequencies among the electronic apparatus, capacitors are requested to be compact yet to have a larger capacitance, a lower ESR (Equivalent Series Resistance) and a lower ESL (Equivalent Series Inductance).
As to the technology for increasing capacitance of a solid electrolytic capacitor (hereinafter referred to as SEC), the U.S. Pat. No. 5,377,073 and the Japanese Patent Laid-open No. H11-274002 disclose a technology of laminating capacitor elements in a chip-type capacitor. Thus the conventional SECs can be increased in the capacitance, and improved in the ESR.
However, when mounting the conventional SECs on the surface of a circuit board like semiconductor components, the SECs need the help of external terminals for connection. This way of connection poses a limitation in the improvement of ESL. In order to further reduce the ESL, shapes and length of terminals for electrical connection and the wirings need to be streamlined. The present invention addresses the above problems, and aims to offer a method for manufacturing large capacitance SECs that can be connected direct with semiconductor components and implement a superior high frequency response.